1. Field of the Invention
The present invention relates to electrical circuits, and, more specifically but not exclusively, to timing circuits in integrated memory circuits, and still more specifically, to timing circuits having a level-shifting circuit.
2. Description of the Related Art
Modern integrated-circuit (IC) design techniques have greatly increased the quantity of transistors on integrated memory circuits and have improved power consumption, e.g., by reducing supply voltages. However, these same techniques have tended to reduce the performance, reliability, and yield of integrated memory circuits due to low supply voltages, threshold-voltage mismatch caused by process variations, etc. As a result, static random-access-memory (SRAM) devices are now commonly designed to operate from at least two supply-voltage sources (a.k.a. “dual rails” or “dual-power rails”). For example, memory cells and word-line drivers on such a device operate at a higher voltage than other electrical components on the device, in order to obtain improved speed, data reliability, and high yields. The other electrical components operate at a lower voltage, in order to reduce leakage currents and power consumption. (See, e.g., U.S. Pat. No. 7,952,939 B2; U.S. Pat. No. 8,164,971 B2; U.S. Pat. No. 8,208,318 B2; U.S. Pat. No. 8,427,888 B2; and U.S. Pat. No. 8,488,396 B2, U.S. Patent Publication No. US 2013/0128655 A1, and Y. H. Chen et al., “A 0.6V 45 nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD_min VLSIs,” 2008 Symposium on VLSI Circuits Digest of Technical Papers, the teachings of all of which are incorporated herein by reference.)
FIG. 1 depicts a schematic diagram of prior-art SRAM 110 implemented in integrated circuit 100. Integrated circuit 100 also comprises logic 120 powered by a supply voltage VDD. SRAM 110 comprises memory array 111 with a plurality of memory cells, level-shifter array 112, word-line (WL) decoder 113 for decoding the address signals to obtain “predecode” signals, control unit 114 for controlling the read/write operations, and input/output (I/O) unit 115 for receiving and transmitting data between the SRAM 110 and logic 120. In addition, various address, clock, and read/write control signals are provided between control unit 114 and logic 120. In order to avoid read/write failures for SRAM 110, the memory array 111 is powered by supply voltage VDDA, which is at a higher voltage level than supply voltage VDD. Word-line decoder 113, control unit 114, and I/O unit 115 are powered by supply voltage VDD, in order to save power. Accordingly, level-shifter array 112 is disposed between word-line decoder 113 and memory array 111, in order to change the voltage levels of signals generated by word-line decoder 113 from the voltage domain of supply voltage VDD to the voltage domain of supply voltage VDDA.
FIG. 2 depicts prior-art word-line driver array 200 having a plurality of dual-power-rail drivers. Word-line driver array 200 is coupled between word-line decoder 202 powered by supply voltage VDD and memory array 204 powered by supply voltage VDDA. Word-line decoder 202 provides a segment signal Ssegment to indicate that one section of the SRAM corresponding to the address signals has been selected. Word-line decoder 202 further provides a plurality of predecode signals (e.g., predecode[0], predecode[1], predecode[2], etc.) to word-line driver array 200 according to the address signals. Each dual-power-rail driver generates a word-line signal according to the corresponding predecode signal and the segment signal Ssegment. In word-line driver array 200, each word-line driver 210, 220, 230 includes a corresponding level-shifter 212, 222, 232 and inverter 214, 224, 234 disposed in the data transmission path. Each level-shifter converts the corresponding received signal from the VDD domain to the VDDA domain.